C SC 481.20 Lecture 12: Link Layer Introduction and Error Detection
major resource: Computer Networking (4th Edition), Kurose and Ross, Addison Wesley, 2008

[ previous | schedule | next ]

Overview

• alternately called link layer or datalink layer
• between network and physical layer
• partitioned into two sublayers:
  • logic link control (LLC) technology-independent "upper" sublayer
  • media access control (MAC) technology-dependent "lower" sublayer
• unit of transmission is called a frame
• focus on communication between 2 "directly" connected nodes
• Link layer is normally associated with LANs (Local Area Networks)
• "directly" is in quotes above because conceptually the LAN is broadcast but physically it may be segmented

Major services/issues

• Framing - packaging the payload
• Channel access - since channel is likely broadcast
• reliable delivery - where have we seen this before?
• flow control - we've seen this issue before too!
• error detection and possibly correction - details below
• Note that few of these services is exclusive to this layer! Why would similar services be provided at multiple layers?
• Most link protocols implemented in hardware
• Host device is Network Interface Card (NIC), aka network adaptor
• Network extending devices include: repeaters, hubs, switches, bridges
• Focus on IEEE 802.x standards for LANs

Error Detection

• signal errors occur as result of interference, attenuation, etc
• addressed at several OSI layers (one of its criticisms)
• concentrate on data link layer here
• error at data link level: 1 bit received as 0, or vice versa
• consider error pattern:
  • single bit : one bit in data unit (e.g. byte, frame)
  • burst : multiple consecutive bits in data unit
  • multiple bit : multiple non-consecutive bits in data unit
• all error detection schemes require redundancy (extra bits)
• Major error detection techniques include:
  • parity - extra bit(s) to make count of 1 bits odd or even
  • checksum - we've already seen this in UDP, TCP, and IP
  • CRC - cyclic redundancy check
  • encoding - each data symbol represented by a unique bit pattern (e.g. ASCII)
• Some detection techniques also permit correction (parity, encoding), depending on configuration

Parity check

• simple parity check
• a.k.a. vertical redundancy check
• append a parity bit to data unit
• even parity: set parity bit so that total # of 1’s in unit (including itself) is even.
• odd parity : similar, only odd
• detects all errors where number of erroneous bits in unit is odd (1,3,5)
• cannot detect even numbers of errors (parity will remain correct)
• Two-dimensional parity check
• a.k.a. Longitudinal Redundancy Check
• parity check over a block of consecutive data units
• each data unit contains simple parity bit (see above)
• additional data unit contains parity bit for corresponding bit position across all data units in block
• cannot detect even numbers of errors in corresponding positions of even numbers of data units. (e.g. units 2 and 4 both have errors in bit positions 5 and 7).
• Concerning the terms vertical and longitudinal: Origins are magnetic tape era. Vertical refers to data stored across the width of the tape (e.g. a byte); longitudinal refers to information stored along its length. Reference: Introduction to Data Communications, by Larry Hughes, Jones and Bartlett, 1997, page 145.

Cyclic Redundancy Check (CRC)

• CRC bits are appended.
• CRC value is such that combination of data and CRC bits form value divisible by "well-known" divisor (the generator polynomial).
• if receiver gets non-zero remainder, error occurred.
• uses modulo-2 division, subtraction, and addition
• CRC generator:
  • start with original data D, r-degree generator polynomial G.
  • append r 0’s (shift left r bit positions) to data, result is D'.
  • divide D' by G, yielding quotient Q and remainder R.
  • add R to D' (using XOR), yielding T.
  • transmit T.
• CRC check by receiver:
  • start with received data T', same generator polynomial G.
  • divide T' by G, yielding quotient Q and remainder R
  • if R is 0 then no error. truncate the last r bits of T' (shift right r positions) and pass on.
  • if R is not 0, then an error has occurred.
• polynomial representation
  • divisor bit string usually expressed as polynomial on x
  • exponent represents bit position and coefficient is bit value (0 or 1).
  • example: string 100101 represented as x5+x2+1.
• there are standard generator polynomials
  • CRC-16 : x16+x15+x2+1 (17 bit generator, yields 16 bit CRC)
  • CRC-ITU : x16+x12+x5+1
  • CRC-32 : (33 bit poly with many terms)
• probability of undetected error is quite small.
• Normally implemented in hardware using shift registers and XOR-gates with feedback. CRC-ITU is 10001000000100001. Corresponds to set of shift registers having 4, 7 and 5 bits, respectively

Error Correction

• Single bit error correction is possible with 2-dimensional parity : parity bits for its row and its column will both be wrong and their intersection identifies the culprit.
• Correction is possible using encodings through Hamming distance and Hamming codes
• Hamming distance
  • given encoding, minimum # bits that must be flipped to change one valid code into another valid code.
  • Example: Hamming distance for ASCII is 1.
  • Example: encoding 1001, 0011, 1100, 0110, 1010, 0101, 0000, 1111 has distance 2 and can encode 8 values.
  • n-bit errors can be detected if Hamming distance is n+1
  • n-bit errors can be corrected if Hamming distance is 2n+1
• Hamming code (1950)
  • allows receiver to determine which bit was flipped.
  • redundancy bits placed in specific bit positions; each represents VRC over specific bit positions
  • assume bit positions numbered starting with 1. Bit positions of redundancy bits are powers of 2 (1,2,4,8,etc). Redundancy bit in position i represents VRC over bit positions whose binary representation has 1 in its bit position i!
  • Example: redundancy bit in position 1 is VRC for all odd-numbered bit positions: 1,3,5,7, etc (binary representation has 1 in position 1). Redundancy bit in position 3 is VRC for bit positions 4,5,6,7 (binary representation has 1 in position 3). Note the overlaps.
  • number of redundant bits r required for unit of m data bits determined by smallest r such that 2r >= m + r + 1