C SC 340 Lecture 1: OS Overview Part 1

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What is an OS?

• provides environment for other programs to operate in
• controls access to system resources
• allocates system resources
• promotes efficient use of system resources
• provides convenient interface for interactive users

Why is it important to say what an OS does not do?

Interrupts

Much OS processing is interrupt driven. An interrupt is an event to which the system responds. Examples of events that cause interrupt:

• completion of I/O operation (hardware interrupt)
• user request for OS service (system call -- software interrupt)
• user exception such as invalid instruction or zero divide (trap)

Each type of interrupt has service routine. Addresses of service routines stored in interrupt vector for fast access -- device and/or interrupt type used as index into vector.

The IBM-PC architecture has specific implementations of interrupt vectors and the associated interrupt request lines (IRQ). See e.g. Webopedia for definitions.

When interrupt occurs:

1. currently executing instruction is completed
2. address of next instruction is saved
3. program counter set to service routine address (from interrupt vector)
4. service routine executed (may have to save/restore registers)
5. program count set to saved address (see step 2)

System Storage Structures

You are familiar with most of the major storage device types: registers, main memory, magnetic disks, optical disks, magnetic tape. Only the first two of these can be directly accessed by the CPU.

Caching

Cache memory refers to a technique rather than a technology. Caching is the temporary storage of information in a faster device to get faster access.

• when memory location requested, its contents copied into higher-access device temporarily
• subsequent requests can be filled from the cache
• this speeds up system operation, especially if large proportion of requests can be met from cache (hit ratio)
• works because of temporal locality principle: a location just used is likely to be used again very soon
• the risk is inconsistency, because now there are two copies of the requested location but only the cached one is updated

memory cache a.k.a. RAM cache resides between the CPU and main memory. Level-1 cache is built into the processor chip itself. Level-2 cache has historically been placed elsewhere on the motherboard but is now being incorporated onto the processor chip as well.

disk cache is RAM memory used to cache data for disk operations. The RAM may reside either on the disk device or be a portion of main memory.

Storage hierarchy

You may be familiar the storage hierarchy from previous courses (CSC 100 or 330). This is a ranking of storage devices based on several factors: access speed, capacity, cost per bit, and volatility. Here are some examples:

• registers - fastest access, highest cost/bit, low capacity, volatile
• main memory - slower access than registers (faster than disks), lower cost/bit than registers (higher than disks), higher capacity than registers (lower than disks), volatile
• magnetic disks - slower access than main memory (faster than tapes), lower cost/bit than main memory (higher than tapes), higher capacity than main memory (lower than tapes), nonvolatile

System I/O Structures

When user process needs to perform I/O, it issues a system call. OS sets the device controller registers accordingly, and device begins work on the operation. When operation is complete, device controller issues interrupt. What should CPU do in the meantime? What should user process do in the meantime? Note that I/O operation is initiated by user system call, completed by controller interrupt.

Assume that while a user process is awaiting I/O, the OS turns its attention to other processes or interrupts (asynchronous I/O). Since several such operations may be pending, OS needs a table to track them. Device status table has an entry for each device, and each entry points to a list of pending requests (containing user, operation, address, #bytes, etc). As each is completed, controller issues interrupt and interrupt handler updates the request list and associated user process.

I/O still requires a lot of CPU attention to transfer data between device buffer and main memory, so a technique called Direct Memory Access (DMA) was developed. Allows this transfer to occur directly w/o CPU intervention; a DMA controller replaces CPU as the "middle man".

A related but distinct technology is memory-mapped I/O. This is technique of reserving main memory address ranges to represent device registers. Allows CPU and device to communicate by reading/writing to main memory. Most well-known example is video.

System Hardware Protection Structures

Any resource sharing can lead to problems. Even on single-user system with only one user process and OS running. What kind of problems?

• a user program tries to read program/data of OS or another user
• a user program tries to write over program/data of OS or another user
• a user program tries to jump into the program of OS or another user
• program error causes device to malfunction
• program error causes "infinite" hold over resource

One protection technique is dual-mode operation. At any instant, the CPU is operating in either user mode or supervisor (privileged, kernel) mode. Indicates whether instruction is carried out on behalf of user or OS. Then define certain instructions, called privileged instructions, that can be carried out only when system in supervisor mode. If CPU sees privileged instruction and mode bit is set to user, issue trap to OS. This allows critical operations to be performed only by the OS. Must assure that user cannot take control while mode bit set to supervisor.

I/O is done this way -- system provides routines called system calls that the user can put in the program, and while the system call is being executed, the mode is changed to supervisor and the I/O operation is performed then the mode is changed back to user before returning.

Another protection technique protects memory space through the use of base register and limit register through which any user memory request must be filtered. Each user has exclusive rights to its logically contiguous address space. Base register contains lowest address of this space and limit register contains size of this space. So memory request must be no less than base register content and less than base+limit. User request outside this range triggers trap to OS. Only OS can set values of base and limit registers.

CPU is protected from infinite user control through the use of timers. When user process gets control of CPU, OS sets timer. If user still in control when timer goes off, OS can replace it.